1. Field of the Invention
The present invention relates to the field of First in First Out (FIFO) buffers, and particularly to a method and apparatus for simultaneously synchronizing information across a boundary between two asynchronous clock domains and for providing an indication of the degree of FIFO fullness to one clock domain in every clock cycle and providing a flag in every clock cycle for the other clock domain indicating the readiness of the FIFO to accept or provide data.
2. Description of the Related Art
FIG. 1 illustrates a prior art approach to transferring data from one clock domain to another clock domain and back. block.sub.-- A 3 represents circuitry in clock domain A (e.g., signals in block.sub.-- A 3 are synchronous to clock.sub.-- A 5 and have reliable data on the rising edge of clock.sub.-- A 5). Similarly, block.sub.-- B 7 represents circuitry and signals that are synchronous to clock.sub.-- B 9. A FIFO 11 is provided between clock domains A and B. In this case, data is being transferred from block.sub.-- A 3 to block.sub.-- B 7 through the FIFO 11. Logic 13, associated with the FIFO, indicates to logic block.sub.-- A 3 that the FIFO 11 is full. This associated FIFO logic 13 also indicates to block.sub.-- B 7 that the FIFO 11 is empty. If the FIFO 11 is full, circuitry in block.sub.-- A 3 stops the transfer of data into the FIFO 11 from block.sub.-- A 3 to prevent overwrite of valid data. Upon a Full indication 15, circuitry in block.sub.-- 7 begins to transfer data into block.sub.-- B 7 until an Empty signal 17 is asserted and received by block.sub.-- B 7. Block B 7 stops reading data from the FIFO 11 upon an Empty signal 17 so that it will not read invalid data (e.g., stale data).
It is evident in this prior art system that logic in clock domain A will not begin to write to the FIFO until it receives an Empty signal 17. Similarly, logic in clock domain B will not read from the FIFO 11 until a Full indicator 15 is received. Thus, there is a latency when the logic in clock domain A waits for a completely empty FIFO 11 before writing and another latency when logic in clock domain B waits until the FIFO 11 is completely full before reading the contents of the FIFO 11.
This prior art approach is satisfactory when both clock domains are relatively slow or when both are equally fast. This prior art is satisfactory when it is not important to have simultaneous FIFO read and write. In other words, for low through put systems, this approach is sufficient. However, in a Sbus ATM (Asynchronous Transfer Mode) system where the ATM is clocked at a much faster rate than the Sbus, prior art methods are no longer sufficient. In order to squeeze Sbus performance to satisfy the demands of ATM, every clock cycle needs to be salvaged. Moreover, when logic in clock domain B (the Sbus side) requires a fast turnaround (e.g., a ATM protocol that requires a 155 megabits per second (Mbps) duplex in an average loaded Sbus 32-bit 32-byte system), this prior art approach becomes inadequate. In a high speed network system, it is imperative to maximize throughput and not wait until the FIFO is 100% full or empty to begin transfer of data into or out of the FIFO. Thus, there is a need for provide varying degrees of fullness or emptiness indications, so as to reduce latency inherent in waiting for a full or empty flag, especially if the FIFO is large.
Furthermore, since logic in clock domain A and logic in clock domain B are asynchronous to each other (e.g., reads and writes to the FIFO are asynchronous), there is a need to dynamically determine at any clock cycle the "true" level of content in the FIFO. For example, if four data words are written to a FIFO by block A and four data words are during the same clock read by block B, there is no net change in the degree of emptiness or fullness of the FIFO.
It is evident that to accurately determine the "true" level of content of the FIFO in any clock cycle, FIFO pointer information from domain B must be synchronized to the clock of domain A, and control information from domain B back to domain A. This information is used to determine the present state or degree of fullness of the FIFO. (e.g., synchronize the signals from the slower clock domain to the faster clock domain).
Information such as control signals, address information, and size information of how much is being written or read from the FIFO may be required to calculate the readiness of the FIFO at each clock cycle (e.g., have enough room or data) to receive or supply from or to an IO DMA slave (e.g., host memory) over the I/O bus.
The prior methods for synchronizing signals from one clock domain to another and back are inadequate for the above-described situations which requires immediate readiness to use the FIFO for data transfer over the IO bus and to maximize throughput for support of high speed networks.
One bit synchronization is not feasible for two reasons. First, as described above, multiple bits of information must be synchronized from one clock domain to another in order to correctly calculate the current level and readiness for data transfer of the FIFO. Second, even if only one bit of information is needed to be synchronized from clock domain A to clock domain B and vice versa, prior art one-bit synchronization schemes have an unacceptable transit time or latency. For example, prior art one-bit synchronization schemes operate on a master and slave principle, and full handshake is required (e.g., a bit of information being synchronized from clock domain A to clock domain B and back from B to A is dependent on information in clock domain B and vice versa.) Thus, a state in clock domain A must not change while the synchronization is taking place (e.g., hold the state of clock domain A while synchronizing a signal from clock domain A to clock domain B).
Furthermore, the now synchronized signal in clock domain B is used for calculations in clock domain B. However, after the calculations and updates have made to the signal, it must now be synchronized back to clock domain A for calculations in clock domain A (e.g., the transit time from one clock domain to another and back exceeds the time constraints of the current application).
Multiple bit synchronization across clock domains introduces unique metastability issues. When data is invalid or uncertain at a particular clock edge (e.g. metastability) in a one-bit synchronization scheme, the true data will eventually reach the correct value (0 or 1) (e.g., a delay is inserted and the correct value is presented at the next clock cycle). Since clock A and clock B are completely asynchronous to each other (e.g., the clocks may be different in phase and frequency), data at a particular clock edge of the synchronizing clock may be unpredictable and unreliable in some instances.
However, when multiple bits are simultaneously being synchronized across clock domains (e.g., a plurality of bits in an address or size information), this metastability problem is exacerbated since two or more bits having unreliable data results in a completely wrong address or size and not simply a delay. In other words, the multi-bit value cannot be trusted at the rising clock edge (i.e., metastability). Thus, prior art methods that require multiple bit synchronization across clock domains typically use techniques (e.g., Grey Code or Johnson Counter) to ensure that a multiple-bit value can only change one bit per clock cycle. These schemes are expensive to implement (e.g., it wastes bits to implement the Grey Code especially if the multiple-bit value is greater than four bits), and the resulting hardware, especially if there are many signals being synchronized across the clock boundaries, is difficult to test and debug.
Thus, there is also a need for a method and apparatus to provide synchronization logic that minimizes the number of bits being synchronized between clock domains and yet provides a true indicator of readiness for data transfer of the FIFO at each clock cycle.